1. Field of the Invention
The present invention generally relates to a field-effect transistor using a compound semiconductor, which is suited to be used in a high frequency band of equal to or more than 800 MHz.
2. Description of the Related Art
A field-effect transistor using a compound semiconductor is generally used for a transmission/reception portion for a high speed/high capacity wireless communication system to amplify a high frequency signal of equal to or more than 800 MHz or to perform switching. An important characteristic required for a high frequency amplifier is a high output characteristic. In order to realize the high output in the high frequency band, it is effective to increase a maximum drain current or attain a high breakdown voltage.
In general, an increase in a doped concentration for increasing the maximum drain current reduces the breakdown voltage. That is, the increase in the maximum drain current and the increase in the breakdown voltage have a trade-off relationship. In view of this, attempts are being made to attain the increase in the maximum drain current and the breakdown voltage both by developing a structure of a transistor.
As an example, in order to increase the breakdown voltage, there is widely used a method of increasing a band gap energy of a semiconductor layer (hereinafter, referred to as “gate contact layer”) which is in Schottky junction with a gate to increase a potential barrier at an interface between a metal and a semiconductor. In a III-V compound semiconductor, aluminum (hereinafter, referred to as “Al”) is added to increase the band gap energy in many cases. For example, in a semiconductor layer mainly containing gallium arsenide (hereinafter, referred to as “GaAs”), an AlGaAs layer is widely used because a lattice matching with GaAs is obtained regardless of an Al composition.
In recent years, a semiconductor layer which mainly contains gallium nitride (hereinafter, referred to as “GaN”) is considered to allow the high breakdown voltage and the high output and is therefore being developed. The semiconductor layer which mainly contains GaN uses an AlGaN layer as a gate contact layer in many cases.
However, a use of AlGaAs or AlGaN as the gate contact layer has a problem of reducing the maximum drain current due to an expansion of a surface depletion layer. A surface of the compound semiconductor generally serves as an interface with a protective insulating film, although the surface has high defect levels, which causes a Fermi level pinning or a transient response of a charge capture/release through the level. As a result, the surface depletion layer is expanded in a case of a direct current or in a frequency band of equal to or more than 1 MHz, which reduces the maximum drain current.
In a GaAs-based transistor, GaAs has a surface level density 10 to 100 times that of silicon. AlGaAs has high defect levels such as a DX center even in a bulk thereof and Al is likely to be oxidized on a surface thereof, so a density of electrons to be captured is significantly larger than that on a surface of the GaAs. Thus, the surface depletion layer is expanded to cause reduction in the maximum drain current. The same phenomenon occurs in a GaN-based transistor.
In view of the above, there has been proposed a field-effect transistor having a structure provided with an unexposed AlGaAs or AlGaN layer, an example of which is a field-effect transistor having a buried gate structure. The field-effect transistor having the buried gate structure includes a buffer layer, a channel layer, a gate contact layer, and a gate electrode. The buffer layer formed of GaAs is provided on a GaAs substrate, the channel layer formed of GaAs is provided on the buffer layer, and the gate contact layer formed of AlGaAS is provided on the channel layer. The gate electrode formed on the gate contact layer is in Schottky junction therewith. A gate buried layer formed of GaAs is provided between a cap layer for ohmic contact, which is formed of n-GaAs, and the gate contact layer. A gate is buried in the gate buried layer and in Schottky junction with the gate contact layer. In general, in order to reduce a resistance of an ohmic region, the gate buried layer and the gate contact layer are each an n-type doping layer. An employment of the buried gate structure increases the maximum drain current (see, for example, JP 2001-185558 A and JP 11-251575 A).
Herein, transistors each having a conventional structure, in which the gate contact layer was exposed, and the buried gate structure were prepared and evaluated with respect to characteristics of two-terminal (i.e., a gate and a drain) breakdown voltage. When a voltage Vdg applied between the gate and the drain was 1 V, 10 V, or 20 V, a gate leakage current Igd (A/mm) in the conventional structure was −3×10−8, −1.5×10−6, or −2×10−2, respectively, while that in the buried gate structure was −1.5×10−8, −5×10−4, or −7×10−2, respectively. Further, the breakdown voltage in the conventional structure was 21 V, while that in the buried gate structure was 31 V. As described above, the buried gate structure has a breakdown voltage higher than that of the structure in which a gate is not buried. However, when the transistor is normally operated, that is, when the voltage applied between the gate and the drain is 10 V or 20 V, the buried gate structure has a problem in that the gate leakage current is increased. This is because a side wall of the gate made of metal is in contact with the buried layer to make a leakage path large. As described above, there is a problem in that a large gate leakage current causes a large gate current to flow in a case of a high frequency operation, which results in a reduction in gate voltage.
In addition, a breakdown voltage leakage current characteristic (i.e., a Vdg value at the time of Igd=0.1 mA/mm) and a drain current (Vd=2V) are determined when a buried layer thickness is changed. The gate leakage current greatly depends on the buried layer thickness. That is, the smaller the buried layer thickness is, the more the leakage current reduces. Note that in a case where the buried layer thickness is small, a distance between a surface and a channel layer where the drain current flows is made short. As a result, the surface depletion layer induces the reduction in the maximum drain current. Therefore, it is difficult for the conventionally proposed buried gate structure to increase the maximum drain current and attain the high breakdown voltage at the same time.